Official launch of the CEA-Leti pilot line within the framework of the European Chips Act

Official launch of the CEA-Leti pilot line within the framework of the European Chips Act
Official launch of the CEA-Leti pilot line within the framework of the European Chips Act

This €830 million initiative, funded equally by participating Member States and Chips JU, will develop five new sets of cutting-edge technologies, including next-generation 10nm and 7nm nodes for FD-SOI.

On November 30, 2023, as part of theEuropean Chips Actthe European Commission officially inaugurated Chips Joint Undertaking (Chips JU), a chip joint venture that aims to bridge the gap between research, innovation and production in the field of semiconductors, notably by launching pilot lines. Calls for funding were then open to organizations wishing to establish pilot lines in Member States.

Last week, on the sidelines of the Leti Innovation Days, the CEA Leti announced the official launch of the pilot line FAMESa pioneering project to advance semiconductor technologies in Europe. This €830 million initiative, funded equally by participating Member States and Chips JU, is aligned with the ambition of theEuropean Chips Act which aims to strengthen the EU’s capacities in semiconductors and to guarantee its technological sovereignty.

© FAMES / Christian Morel

The pilot line will develop five new sets of technologies, namely next-generation 10nm and 7nm nodes for FD-SOI, several types of embedded non-volatile memories (OxRAM, FeRAM, MRAM and FeFET), radio frequency components ( switches, filters and capacitors), two 3D integration options (heterogeneous integration and sequential integration), and miniature inductors to develop DC-DC converters dedicated to power management integrated circuits (PMICs). ​

These five technologies are expected to create market opportunities for low-power microcontrollers, multiprocessor units (MPUs), advanced AI and machine learning devices, intelligent data fusion processors, RF devices, chips for 5G/6G, automotive chips, intelligent sensors and imagers, and new components for space.

Invented by CEA-Leti, FD-SOI is a planar Cmos technology which offers the best PPAC-E (Performance, Power, Surface, Cost and Environmental Impact) for mixed circuits which mix digital, analog and radio-frequency blocks, recalls the French R&D organization, which specifies that FD-SOI has been adopted by world leaders in semiconductors because of its strict electrostatic control at the transistor level and because it is well suited to energy management technologies .

The booming FD-SOI market is therefore awaiting the next-generation 10nm and 7nm nodes, assures CEA-Leti, which lists no fewer than 43 companies throughout the electronic systems value chain – from materials suppliers and equipment manufacturers to fabless companies, including CAD software publishers, integrators, equipment manufacturers and end users in the ITC, automotive, medical, space and security markets – having formally expressed their support for the FAMES initiative, foreshadowing a dynamic ecosystem of start-ups, SMEs and global industry leaders.

“By integrating and combining a set of cutting-edge technologies, the FAMES pilot line will open the door to revolutionary system-on-chip architectures and provide smarter, greener and more efficient solutions for future chips, with the FAMES project granting a particular attention to the sustainability issues of semiconductors »underlines Jean-René Lèquepeys, technical director of CEA-Leti.

“Chips JU is proud to contribute to this strategic initiative and to strengthen EU sovereignty in a critical area. This pilot line […] will promote collaboration between several European actors”says Jari Kinaret, executive director of Chips JU. Chips aims to act as a catalyst and model for new public and private collaborations in key areas.”

In addition to CEA-Leti, coordinator of the pilot line, the FAMES consortium brings together imec (Belgium), Fraunhofer Mikroelektronik (Germany), Tyndall (Ireland), VTT (Finland), CEZAMAT WUT (Poland), UCLouvain (Belgium), Silicon Austria Labs (Austria), the SiNANO Institute (France), Grenoble INP-UGA (France) and the University of Granada (Spain).

​The pilot line will be accessible to all EU stakeholders (academia, RTOs, SMEs and industrial companies) and all like-minded countries through annual open calls and on request, following a fair and non-discriminatory selection process.

© FAMES

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