Stanford researchers are exploring new technology that could improve the internal caches of current CPUs and graphics processors. They are working on hybrid gain cell memory – a clever mix of SRAM and DRAM technology – designed to solve the problems that SRAM caches currently face.
Professor Philip Wong, who leads the project and teaches electrical engineering at Stanford, highlights a major challenge in modern GPU design: the “memory wall problem.” This problem concerns the difficulty and high energy cost of transferring data from the slower DRAM to the faster but smaller SRAM cache. This bottleneck prompts researchers to look for substitutes for SRAM with better performance.
SRAM size is another issue. Current chips use a lot of space for SRAM, which occupies six transistors per bit (four to store data and two to handle access). In contrast, DRAM can store data with a single transistor and a few additional components, but it has the disadvantage of needing to be constantly refreshed to keep the data alive.
This is where hybrid gain cell memory comes in, which promises considerable advantages:
- Increased storage density: The main advantage of gain cell memory is that it allows for increased storage capacity, which is crucial for low-level caches.
- Improved performance: Larger caches reduce the time it takes to transfer data from the system’s DRAM to the CPU or GPU, thereby improving overall performance and reducing latency.
- Power Efficiency: The technology promises to address power consumption issues associated with current cache architectures.
Researchers believe this technology could revolutionize future CPU and GPU designs, pushing low-level cache capabilities beyond what is possible today.
Additionally, hybrid gain cell memory works well with 3D stacking techniques, like AMD’s 3D V-Cache, paving the way for even greater capacity increases. This combination could have a significant impact on processor performance across a range of computing tasks.
If things go as planned, this research could usher in a new era in computer architecture, solving some of the speed and efficiency problems that have long held back modern systems.
