With the Xeon 6P “Granite Rapids” processor, which it is starting to deliver to server manufacturers after talking about it for months, Intel aims to stop losing market share in the data center to its competitor AMD. Its main argument is to also provide a very large number of cores and a lot of cache memory, which makes it possible to reduce the quantity of servers in a data center and, therefore, its energy costs.
According to analysts, the advantage of the previous Xeons over the AMD Epycs was that Intel’s chips were delivered in larger quantities. Understand with less downtime than the competing processor, which systematically battles against Apple and Nvidia to find a place on the factory lines of TSMC, their common manufacturer.
The interest of this new Xeon would be a return to innovative design. Jumbled together, we note a “chiplet” architecture, very fine engravings and faster interconnections than elsewhere between the circuits, for configurations which should be more versatile. In short, with this sixth generation, the Xeon would no longer be a default choice.
Concerning the general performance of the 6900P models, Intel communicates figures: with twice as many cores as the high-end Xeon 5, the Xeon 6P would be twice as efficient on all applications and up to three times more efficient on generative AI algorithms (Intel takes inference algorithms on the LLM Llama2-7B as an example).
The AMX and AVX-512 mathematical acceleration units integrated into each core would increase the indexing of data in a vector base by 2.71 times and its search by 7.34 times compared to code executed by the base x86 instruction set . However, using SVS libraries in the code of generative AI applications.
A first series of very high-end models
Detailed for at least a year, at the risk of undermining the promotion of the Xeon 5, launched at the beginning of this year, the Xeon 6 is available in two families. The “Sierra Forest” version has been delivered since this summer to hyperscalers to run web-native applications in containers. It is made up of 144 very energy-efficient “E-Core” cores. They lack AVX-512 and AMX circuits accelerating the most complex math functions and the ability to execute two streams of instructions simultaneously. We now know that this first series of Xeon 6700E will soon be supplemented by a Xeon 6900E series which will offer the record quantity of 288 cores.
The second family, the one that Intel is launching today to equip business servers, is made up of 128 high-performance “P-Core” cores. They have all the options, particularly those that accelerate generative AI processing. The version launched these days is numbered 6900P, because, like the 6900E, it should consume 500W per chip. Intel is expected to launch a 6700P version in 2025 with 96 “P-Cores” which will consume, like the current Xeon 6700E, 350W per chip.
The 6900P model consists of three circuits, each containing 48 cores. The 6700P model will only have two of these circuits. Intel is talking about the future arrival of a version containing only a single 48-core circuit (probably numbered 6500P) and even a version with a shortened circuit with only 16 cores (6300P?). Variants of these designs are respectively called UCC (Ultra Core Count), XCC, HCC and LCC (Low Core Count). The smallest version would only consume 150W per chip.
Please note that the number of cores indicated corresponds to the quantity of cores actually engraved, but, as is customary in semiconductors, not necessarily to the number of functional cores. Like AMD, Intel declines circuits that do not pass all the tests into versions with fewer functional cores, less expensive, but not necessarily less energy-consuming. In fact, the founder made the decision to compensate for the reduction in the number of cores by an increase in their frequency.
Intel therefore plans the following variations:
- 6980P: 128 functional cores running 256 threads, clocked between 2 and 3.2 GHz,
- 6979P: 120 functional cores running 240 threads, clocked between 2.1 and 3.2 GHz,
- 6972P: 96 functional cores running 192 threads, clocked between 2.4 and 3.5 GHz,
- 6960P: 72 functional cores running 144 threads, clocked between 2.7 and 3.8 GHz
- And 6952P: also 96 functional cores running 192 threads, but underclocked between 2.1 and 3.2 GHz to consume only 400W, or 100W less than the others.
The announced prices are very high-end: from $8,000 for the 6960P to nearly $25,000 for the 6980P. The high-end models of the previous generation, that of the Xeon 5, range between 6000 dollars for the threads at 1.9 GHz).
It is notable that Intel is not announcing a maximum of 96 functional cores on the future 6700P version, but only 86. We do not know why. On the previous version, Intel had also announced that the Xeon 5 would have a maximum of 56 functional cores, before changing its mind a little later by discreetly presenting a version with all 64 functional cores. We can bet that the foundry company has to be careful with the success of its industrial processes which are still in progress.
Better than the Epyc 9004, except on consumption
One of the big new features of the Xeon 6 is in fact that the circuits containing the cores are engraved by the founder’s brand new “Intel 3” industrial chain with a finesse, we are told, of 5 nanometers. It would be as efficient in terms of electrical resistance (i.e. heat dissipation and energy consumption) as the 3 nm engraving from which AMD will benefit for its next “Turin” generation of Epyc processors (probably revealed next week).
In fact, compared to the previous generation of Xeon, the number of cores engraved is doubled, while energy consumption is only multiplied by 1.4.
That said, if we compare with AMD’s current high-end Epyc 9004 processors, from 64 to 96 cores, their consumption ranges from 280 to 400W. It’s better. AMD has also offered two Epyc 9004s with 128 cores since this year and whose consumption peaks at 360W. However, these processors have less cache (256 MB compared to 1152 MB for the 96-core one) and one of them only executes one thread per core, the equivalent of a 64-core model.
In the Xeon 6, the circuits containing the cores each integrate four DDR5 memory controllers. These support new MRDIMM memory modules developed by Micron which are said to be 1.6 times faster than ordinary DDR5 modules. There is also a 504 MB cache memory. The high-end 64-core Xeon 5s peaked at 320 MB cache and those with 32 cores peaked at 160 MB cache.
On the chip, there are also two other circuits, etched with a precision of 10 nm (“Intel 7” chain), which contain the PCIe 5.0 bus controllers. These provide access to 136 PCIe lanes on single-socket servers, but this number drops to 96 lanes if the server contains two, four or eight sockets.
For the record, a GPU consumes sixteen PCIe 5.0 links and an NVMe SSD currently consumes two, or four if it is a new generation in NVMe 2.0. 64 PCIe lanes can be used in CXL 2.0, a kind of ultra-fast network that allows expansion cards, NVMe SSDs and even server RAM to be placed on a remote machine. The Xeon 5 and the current AMD Epyc 9004 only support the CXL 1.1 protocol which only works well with remote NVMe SSDs.
Alongside the PCIe controllers are accelerators supposed to streamline the decoding of data packaged in a protocol. However, Intel does not say that these accelerators can replace real DPUs (which Intel calls IPU) which remain particularly useful for managing communications on RoCE (RDMA-over-Converged Ethernet) networks. These are increasingly necessary to communicate with high-speed storage arrays in AI applications.
